The present invention relates to a high density multichip package, and specifically to a power feed structure therefor.
As typically shown and described in IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-6, No. 2, June 1983 entitled "Multilayer Substrates with Thin Film Fine Lines Generated by the Ground Layer Oxidation (GLO) Process" by Akihiro Dohya et al, the recent tendency is toward packaging a plurality of LSI (large scale integration) circuit chips on a single ceramic substrate which is provided with a plurality of contact pads on the outer portion thereof and conductive patterns for coupling the contact pads to the circuit chips. The package is mounted on a printed circuit board which includes an array of connector pins respectively engageable with the contact pads. Some of the connector pins are connected to an external power source while others are connected to an external circuit.
In addition to the tendency toward circuit integration and packaging, needs for high speed signal processing and low level signal transmission have imposed requirements that voltage deviations from circuit to circuit be reduced to a minimum. From this standpoint, the above-mentioned multichip package is not satisfactory. More specifically, since the power supply is provided exclusively from the outer periphery of the substrate there is a voltage difference between the LSI chips in the outer portion of the substrate and those in the inner portion.